1. Field of the Invention
The present invention relates to a silicon wafer where both slip dislocation and warpage occurrence are suppressed, and to a method for manufacturing the same.
2. Background Art
Silicon wafers used as a substrate for a semiconductor devices or the like are manufactured by slicing a silicon single-crystal ingot into wafers and performing heat treatment, mirror finishing, and other processing steps to form a finished wafer. One method for manufacturing silicon single-crystal ingots is the Czochralski method (“CZ method”), for example. The CZ method is used for the majority of silicon single-crystal ingot manufacturing because of the ease of obtaining single-crystal ingots with large diameters, and because defects can be controlled relatively easily.
A silicon single-crystal (“CZ-Si”) pulled by the CZ method includes crystal defects called “grown-in defects”. The CZ-Si contains interstitial oxygen in a supersaturated state, but the supersaturated oxygen causes formation of fine defects called Bulk Micro Defects (hereinafter, “BMD”) in heat treatment (anneal) conducted thereafter.
In order to form a semiconductor device on a silicon wafer, it is required that no crystal defects are present in the device forming region. The reason for this requirements is that when crystal defects are present on a surface on which a circuit is formed, circuit breaks or other device problems are caused by the defects. On the other hand, it is required that the silicon wafer contains BMDs in a proper amount. This is because the BMDs serve to getter metal impurities or the like which cause semiconductor device malfunction.
In order to satisfy the abovementioned requirements, a high-temperature annealing process has been developed which induces BMDs to form inside the silicon wafer to provide an Intrinsic Gettering layer (“IG layer”), and which diminishes grown-in defects present in the surface of the silicon wafer to form a Denuded Zone (“DZ”) where crystal defects are sharply reduced. Specifically, a method has been proposed for performing a high-temperature anneal on a nitrogen-doped substrate to reduce grown-in defects on the surface of the substrate, and to form BMDs including nitrogen as nuclei inside the substrate in JP-A-10-98047.
However, the oxygen concentrations in DZ layers formed on both front and back surfaces of silicon wafers in the abovementioned high-temperature anneal process are lowered considerably due to outward diffusion of oxygen during heat treatment. As a result, restraint of dislocation defect extension on the wafer front and back faces is significantly reduced, and dislocation defects (“slip defects”) easily propagate into the bulk from fine flaws on the front and back surfaces created in the anneal step, which results in lowering the strength of the silicon wafer due to propagation of slip dislocations. For example, when a silicon wafer is annealed while being supported by a heat treatment susceptor or the like, slip dislocations may often extend from the area proximate a portion of the back surface where the wafer is supported by the susceptor. Further, that slip dislocations may extend from an edge portion of the silicon wafer.
When the strength of the silicon wafer is reduced, the wafers may be damaged or broken during subsequent manufacturing steps. However, the DZ layer is essential for semiconductor device formation, and silicon wafers having DZ layers while also having excellent strength properties have been required.
In the conventional method described in JP-A-10-98047, reduction in the strength of silicon wafers has not been addressed, and therefore propagation of slip dislocations is unavoidable in silicon wafers manufactured by such methods.
JP-A-2006-40980 discloses a method for generating BMDs at a high density in order to prevent occurrence of slip dislocations. Specifically, a silicon wafer manufacturing method is disclosed where oxygen precipitation nuclei with sizes of 20 nm or less in the amount of 1×1010 atoms/cm3 or more are formed in the BMD layer by heat treating a substrate sliced from a silicon single-crystal ingot under an atmosphere of nitrogen gas, inert gas, or mixed gas of ammonia gas and inert gas at a temperature of 500 to 1200° C. in a range of 1 to 600 minutes, with rapid heating and cooling ramps. A silicon wafer where BMDs with a high concentration of 1×1010 atoms/cm3 to 1×1012 atoms/cm3 have been generated by repeating heat treatment steps several times, as disclosed in JP-A-08-213403.
In recent years, however, since silicon wafers have increased in diameter, and rapid temperature ramping in a Rapid Thermal Annealer (“RTA”) is frequently used, in addition to the occurrence of slip dislocation, warpage generated in the wafers becomes problematic.
An illustration of slips and warpage introduced by the RTA heat treatment is shown in FIG. 1. Slips are introduced from contacting points between a wafer back face and the wafer support. The slips extend in a 110 direction, which causes wafer damage or even breakage in some cases. Warpage is a phenomenon where a wafer is deformed due to thermal strain during the RTA heat treatment. For example, hill-shaped portions and valley-shaped portions appear on a wafer of 100-plane, as shown in FIG. 1. Warpage of a silicon wafer before heat treatment is generally 10 μm or less. However, when a heat treatment such as RTA is performed on the silicon wafer, a difference in height between a hill and a valley on the silicon wafer may reach several tens of μm. When the warpage becomes large, a semiconductor device pattern cannot be accurately exposed on a wafer surface, which causes lowering of semiconductor device yield. The problem of warpage becomes especially significant when the wafer diameter reaches 200 mm or more, and it is impossible to avoid the problem only by establishing a high BMD concentration.